1. Technical Field
The present disclosure relates to a test apparatus and method and, more particularly, to an apparatus and method for testing the input/output circuit characteristics of a device under test (DUT) by using an eye mask generated in a test apparatus.
2. Discussion of the Related Art
In recent years, as the operating speeds of semiconductor devices, such as memory devices, have increased more testing requirements therefor are required. For instance, apparatuses that test semiconductor devices are also needed to operate at high speeds in accordance with the trend toward the high operating speeds of the semiconductor devices. However, in most cases, the operating speeds of the test apparatuses do not match the operating speeds of the semiconductor devices, and manufacturing costs are significantly increased in order to raise the operating speeds of the test apparatuses to match the operating speeds of the semiconductor devices.
FIG. 1 is a block diagram of a system for illustrating a conventional method of testing the performance of a semiconductor device 20, that is, a device under test (DUT), by using a tester 10, which is a general automatic test equipment (ATE) machine. The semiconductor device 20, such as a semiconductor memory device, typically includes an input/output (I/O) circuit 21, a memory core 22, and a control logic circuit 23.
More particularly, since the I/O circuit 21 of the semiconductor device 20 operates at high speeds, the operating characteristics of the I/O circuit 21 are tested by a system using the conventional method of FIG. 1. To test the operating characteristics of the I/O circuit 21, the tester 10 applies a test pattern to the semiconductor device 20. The test pattern applied to the semiconductor device 20 is output as a signal from the I/O circuit 21 of the semiconductor device 20 and returned back to the tester 10.
U.S. Pat. No. 6,629,272 discloses a bit error rate tester (BERT) that is an example of a conventional test apparatus that tests semiconductor devices. In the BERT, a test pattern is generated by a pattern generator and applied to a DUT, and signals output from the DUT are applied to an error detector. Then, the bit error ratio (BER) of each signal output from the DUT is compared with a BER generated in the error detector so as to detect an error.
US Patent Laid-Open Publication No. 2003-0097226 discloses another example of a conventional test apparatus that compares a binary coded pulse signal received via a transmission line with a voltage threshold window to determine the voltage of the pulse signal. The conventional test apparatus is programmed to use a maximum voltage Vmax and a minimum voltage Vmin as input values and to generate the voltage threshold window that is switched between the maximum voltage Vmax and the minimum voltage Vmin.
As described above, it is difficult to increase the operating speeds of conventional test apparatuses to match the increased operating speeds of semiconductor devices. It is possible, however, to allow a test apparatus to more easily test semiconductor devices using an eye mask. If the eye mask is generated by programming a maximum voltage and a minimum voltage in a software program, however, a lot of time is required, thus precluding any benefits from being obtained by such testing of a high-speed semiconductor device at high speeds.